A Hybrid Low Power Fast Full Adder Using XOR And XNOR Gates

Abstract

In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. Many existing XOR-XNOR cells suffer from non full-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR XNOR cell, is presented. In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide– semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel fullswing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs.