Implementation of Rounding Based Approximate Multiplier Using Radix Encoding Techniques
The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. In this paper, To focus on hardware-level approximation by introducing the partial product perforation technique for designing approximate multiplication circuits. In this is prove in a mathematical rigorous manner that in partial product perforation, the imposed errors are bounded and predictable, depending only on the input distribution. Through extensive experimental evaluation, to apply the partial product perforation method on different multiplier architectures and expose the optimal architecture– perforation configuration pairs for different error constraints. The proposed multiplier can consume 58% less energy/op with average computational error of ~1%. Finally, a small computational error does not ably impact the quality of DSP and the accuracy of classification applications.