Design of counter based wallace tree multiplier using symmetric stacking

  • V. Marimuthu PG Scholars, Department of Electronics and Communication Engineering, Nandha Engineering College (Autonomous), Erode, India.
  • P. Sukumar Professor, Department of Electronics and Communication Engineering, Nandha Engineering College (Autonomous), Erode, India.
Keywords: Counter, high speed, low power, multiplier, Wallace tree.

Abstract

High speed, efficient addition of multiple operands is an essential operation in any computational unit. The speed and power efficiency of multiplier circuits is of critical importance in the overall performance of microprocessors. A new binary counter design is proposed. It uses 3-bit stacking circuits, which group all of the “1” bits together, followed by a novel symmetric method to combine pairs of 3-bit stacks into 6-bit stacks. The bit stacks are then converted to binary counts, producing 6:3 counter circuits with no xor gates on the critical path. This avoidance of xor gates results in faster designs with efficient power and area utilization. In VLSI simulations, the proposed counters are 30% faster than existing parallel counters and also consume less power than other higher order counters. Additionally, using the proposed counters in existing counter-based Wallace tree multiplier architectures reduces latency and power consumption for 64 bit multipliers.

Published
2018-12-03